I’m in agreement with all of the above.
I haven’t looked into the LowerTypes pass in Scala, but I’m starting to think it is worth porting that to CIRCT. In the longer term, as you mention, we might go different directions. But, pragmatically speaking, we are already hitting paths within CIRCT that get hung up on how to handle FIRRTL aggregate types, and I would like to unlock these paths in a way that isn’t “hacky”. Porting the LowerTypes pass to the FIRRTL dialect seems like a clear way to unlock emitting System Verilog, lowering to LLHD, and lowering to RTL with the current state of CIRCT.
Maybe we don’t lean on this pass in the long term, but for now, it seems like a well-defined and not “hacky” way to unlock this functionality. I’d be interested in working on this if we agree it is a worthwhile addition (and no one else is already looking into it).
I do see how the RTL dialect should hopefully emerge as a “nexus” dialect that circuits go through, so perhaps it is worth discussing what it would look like to go from FIRRTL aggregates to the RTL dialect. We could lower aggregates within FIRRTL first, as discussed above. Or, we could come up with a way to represent this in RTL. Would a representation like bundles (as Fabian mentioned) make sense? Would it make sense to depend on the SV dialect in the RTL dialect and use the proposed SV interfaces? I’m curious to flesh out what the ideal solution will look like in the long term, even if we are making more pragmatic decisions in the short term.