Topics tagged riscv

Topic	Replies	Views	Activity
When adding intrinsic in riscv，the command line option -target-feature fails to set the corresponding feature of subtarget to true, resulting in an error, so how to enable the feature correctly? Beginners riscv , clang , llvm	5	302	April 23, 2024
Questions about the T-Head Vector extension (xtheadvector) in LLVM upstream LLVM Project riscv , llvm	10	317	April 16, 2024
Error encountered while compiling clang and OpenMP for RISC-V target LLVM Project riscv , llvm	7	87	April 16, 2024
RISCVInsertVSETVLI doLocalPass RISCV riscv	1	59	April 15, 2024
Question about adding a RISCV intrinsic Beginners riscv , llvm	0	86	March 20, 2024
Build problem in LLVM Beginners riscv , clang , llvm	2	1134	March 15, 2024
Enforce consecutive physical register allocation Beginners riscv , llvm	2	118	March 13, 2024
Scheduler Question :Understanding Scheduling Components in the RISC-V Backend for Dual-Issue Processor Support LLVM Project riscv , llvm	1	100	March 9, 2024
Dual-Issue Schedule in RISCV LLVM Project riscv , llvm	0	88	March 8, 2024
Is RV64 + ELEN=32 valid? RISCV riscv , clang	2	100	March 8, 2024
RISC-V induction variable substitution Loop Optimizations riscv	1	85	March 5, 2024
User guided RISC-V hint-instruction injection with pragmas using a clang plugin Beginners riscv , clang , llvm	0	64	February 23, 2024
How to extend live interval to some instruction? Beginners riscv , llvm	0	112	February 23, 2024
PMDataManager segfault when using `addRequired` in custom compiler pass Beginners riscv , llvm	1	114	February 22, 2024
Compiling U-BOOT for RISCV fails with LLD LLD riscv , clang , llvm	1	147	February 17, 2024
Memory-to-memory instructions support Beginners core , riscv , clang	1	183	February 13, 2024
Detect rvv instruction using BOLT pass BOLT riscv	2	206	February 11, 2024
Directly referencing a basic block MLIR riscv , llvm	1	122	February 1, 2024
Deal with riscv fixup for a custom target supporting bundle instructions RISCV riscv	0	126	January 31, 2024
What is the default rvv register bits length for code generation? How about the LMUL choice support status for rvv codegen in LLVM? RISCV riscv	7	605	January 29, 2024
Trouble adding LLVM intrinsic for custom RISCV hardware RISCV riscv , llvm	6	197	January 28, 2024
How to mapping Intrinsic function to multiple riscv instruction? RISCV riscv	10	363	January 25, 2024
[RFC] VCIX Dialect MLIR riscv	10	768	January 19, 2024
CSR support for embedded RISC-V target -- T-Head E907 Beginners riscv	0	83	January 18, 2024
[Query] gwp_asan Support for RISC-V LLVM Project riscv	0	61	January 3, 2024
[RFC] prestacked annotation to solve risc-v interrupt stacking mess RISCV rfc , riscv	3	667	October 29, 2023
[RFC]: Strengthen Relaxed Atomics Implementation behind `-mstrict-rlx-atomics` Flag Code Generation arm , arm64 , powerpc , riscv , llvm	28	1458	December 22, 2023
Will the embedded assembly code be scheduled normally? RISCV riscv	0	169	December 22, 2023
Merging RISCVToolChain and BareMetal toolchains Clang Frontend riscv , clang	3	291	December 11, 2023
How to convert between fixed length vector and scalable vector for RISC-V backend? MLIR riscv , llvm	2	189	December 8, 2023