Code Generation

Topic	Replies	Views	Activity
How to affect registers to make macro fusion happen Code Generation	2	89	March 7, 2023
Legalizing: integer promotion with custom expand Common Infrastructure	3	80	March 4, 2023
Tablegen: add custom field to Instruction description Common Infrastructure	2	92	March 3, 2023
Global ISel Common Infrastructure	7	211	March 3, 2023
Using MacOS calling convention to call external functions AArch64	4	134	March 2, 2023
Global Isel? RISCV	1	157	March 2, 2023
Running passes added by addPassesToEmitFile() mutates a module Common Infrastructure	2	69	March 2, 2023
RISC-V LLVM sync-up call 2nd March 2023 RISCV	0	162	March 1, 2023
SysV ABI non-power-of-two returns, motivation? X86	0	81	February 27, 2023
Handling PHIs in Uniformity Analysis AMDGPU	3	156	February 23, 2023
What do extra operands of COPY mean? Code Generation	4	141	February 22, 2023
Why is REG_SEQUENCE lowered during TwoAddressInstructions? Common Infrastructure	3	118	February 22, 2023
[RFC][DwarfDebug] Fix and improve handling imported entities, types and static local in subprogram and lexical block scopes Common Infrastructure debuginfo	0	241	February 17, 2023
[RFC] Syncing Asm Goto with Outputs with GCC Common Infrastructure llvm	12	1097	February 17, 2023
How to test an individual instruction? Code Generation	5	83	February 17, 2023
Tablegen: Deleting deprecated positional instruction-operand matching support Code Generation	0	111	February 16, 2023
How to add a customed argument in llc? Code Generation	1	68	February 16, 2023
RISC-V LLVM sync-up call 16th February 2023 RISCV	0	160	February 15, 2023
Is there any way to run a pass before AsmPrinter? Code Generation	2	88	February 15, 2023
[AMDGPU][LLC][LLVM] Cannot select: intrinsic %llvm.amdgcn.if AMDGPU llvm , gpu	0	182	February 14, 2023
Support for "zicsr" and "zifencei" extensions RISCV	5	463	February 13, 2023
Is lldb for riscv ready to use? RISCV	3	330	February 13, 2023
Catching up on uniformity analysis AMDGPU llvm , amdgpu	5	149	February 13, 2023
Question about register spilling, rematerialization, and racy accesses Code Generation llvm , regalloc	3	217	February 10, 2023
Resource MII computation in MachinePipeliner Common Infrastructure	1	105	February 10, 2023
Changes to MCInstrDesc and tablegenned instruction tables (was Re: Impact of default PIE on llvm testing times) Common Infrastructure	3	218	February 10, 2023
Lld link newlib nano show out of range error for _printf_float RISCV	0	112	February 10, 2023
Link failed using riscv clang for rv64imac arch RISCV	7	192	February 10, 2023
Is anyone able to build libcxx/libcxxabi for riscv RISCV	0	82	February 9, 2023
ELF mergeable sections Common Infrastructure	4	125	February 9, 2023