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Reminder: Zoom link changed
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0
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131
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January 5, 2022
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Targeting Non-Verilog Backends
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4
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298
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July 22, 2021
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Why we need a staticlogic dialect?
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2
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171
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December 23, 2021
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CIRCT Bay Area Meetup (December 2021)
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5
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279
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December 15, 2021
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Can we use circt to generate netlist?
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2
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187
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December 9, 2021
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Using Moore to compile to LLHD dialect
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1
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388
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November 19, 2021
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Writing `sv.verbatim` output to separate file
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4
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123
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November 17, 2021
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Basic TOSA support
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6
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441
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November 16, 2021
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Using hw.uarray
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9
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197
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November 15, 2021
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[Torch-MLIR Community Meeting] 2021-11-11
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0
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214
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November 10, 2021
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LLVM-MOS Backend
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2
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203
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November 7, 2021
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Unsupported by backend lowering: `torch.operator` op
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2
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272
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October 28, 2021
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Aten::gelu is not a registered op
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1
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135
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October 22, 2021
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CIRCT Bay Area meetup
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2
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171
|
October 13, 2021
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CROSS HW Section
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2
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144
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October 12, 2021
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Graduating mlir-npcomp -> torch-mlir
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4
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658
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September 24, 2021
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Infrastructure for converting Standard to Comb or primitives with Scheduling information
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20
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367
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September 23, 2021
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Looking for CIRCT projects and mentors for Outreachy (Sept 23)
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0
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186
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September 20, 2021
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Symbols for wires, regs, and instances
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3
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207
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September 11, 2021
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[PSA] LLVM submodule URL change
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1
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126
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September 10, 2021
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Calyx test failure
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2
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126
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September 10, 2021
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SystemVerilog wire names
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8
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270
|
September 9, 2021
|
|
Verilog Emission docs
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0
|
176
|
September 3, 2021
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|
Target Triples for Hardware Compilers
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3
|
278
|
August 27, 2021
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Calyx + CIRCT meeting
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4
|
229
|
August 26, 2021
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[FIRTOOL] automatic in always block
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3
|
169
|
August 24, 2021
|
|
`InstanceLike` and `ModuleLike` interfaces
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2
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142
|
August 20, 2021
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[FIRTOOL] Register Verilog emitter
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3
|
158
|
August 18, 2021
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[FYI] Windows builds on push to main
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0
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101
|
August 13, 2021
|
|
Comb MuxOp 2:1 vs N:1
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18
|
281
|
August 11, 2021
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