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Is there an op in the calyx dialect that maps invoke?
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6
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238
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October 20, 2022
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Is there some way to run the calyx dialect
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2
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177
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October 19, 2022
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Integration with ABC optimizer
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3
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416
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October 17, 2022
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Unsupported by backend contract: module initializers
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1
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230
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October 11, 2022
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Torch.empty_like supported in torch MLIR
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3
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227
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October 11, 2022
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[Community Meeting / Developer Hour] Refactoring recurring meetings
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2
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939
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October 4, 2022
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Firtool fails on chisel-circt-demo
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4
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314
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September 28, 2022
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TorchDynamo Developer Hour Slides and Notes
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4
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979
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September 28, 2022
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Circt-opt gives error for the input mlir (in core dialects) - which was generated by the firtool from the .fir file corresponding to the standard GCD tester
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2
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116
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September 21, 2022
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Is it feasible to convert "pipeline" dialect" to "FSM" directly?
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3
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216
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September 14, 2022
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WOSET'22 call for papers
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1
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274
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September 9, 2022
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Torch-mlir to TOSA
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4
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370
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September 7, 2022
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Latency-Insensitive Finite State Machine
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4
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267
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August 30, 2022
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Enzyme Annual Meeting
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2
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267
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August 25, 2022
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[ESI (ostensibly)] On memory services/streams
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1
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221
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August 23, 2022
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CIRCT now in Compiler Explorer (godbolt.org)
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2
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568
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August 4, 2022
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[Torch-MLIR Community Meeting] 2022-08-01
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1
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409
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August 2, 2022
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Announcing Torch-MLIR Office Hours
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1
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352
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July 22, 2022
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LLVM / Pull request discussion
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0
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247
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July 21, 2022
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[Asia-Friendly Developer Hour] MHLO support!
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4
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555
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July 18, 2022
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Lack of constructs with a sensitivity list
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10
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269
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July 16, 2022
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FPGA development for a newbie?
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3
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492
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July 7, 2022
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[RFC] Representing pipelined loops
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31
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1208
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July 7, 2022
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Is there something like sv.logic instead of sv.reg/sv.wire?
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5
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438
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July 1, 2022
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ExportVerilog simplification for pretty-printing output verilog
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8
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333
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June 29, 2022
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[Comb][ExportVerilog] Add an operation to swap bits
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2
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199
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June 23, 2022
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[RFC] Stream Dialect
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21
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714
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June 23, 2022
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Build failed for CIRCT project
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5
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197
|
June 13, 2022
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[Torch-MLIR Community Meeting] 2022-06-06
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0
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197
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June 6, 2022
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First results from using LLVM CIRCT on our design
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6
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497
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May 19, 2022
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