Using Moore to compile to LLHD dialect
|
|
1
|
499
|
November 19, 2021
|
Writing `sv.verbatim` output to separate file
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4
|
215
|
November 17, 2021
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Basic TOSA support
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6
|
917
|
November 16, 2021
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Using hw.uarray
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9
|
304
|
November 15, 2021
|
[Torch-MLIR Community Meeting] 2021-11-11
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0
|
339
|
November 10, 2021
|
LLVM-MOS Backend
|
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2
|
469
|
November 7, 2021
|
Unsupported by backend lowering: `torch.operator` op
|
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2
|
547
|
October 28, 2021
|
Aten::gelu is not a registered op
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1
|
302
|
October 22, 2021
|
CIRCT Bay Area meetup
|
|
2
|
243
|
October 13, 2021
|
CROSS HW Section
|
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2
|
225
|
October 12, 2021
|
Graduating mlir-npcomp -> torch-mlir
|
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4
|
918
|
September 24, 2021
|
Infrastructure for converting Standard to Comb or primitives with Scheduling information
|
|
20
|
633
|
September 23, 2021
|
Looking for CIRCT projects and mentors for Outreachy (Sept 23)
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0
|
291
|
September 20, 2021
|
Symbols for wires, regs, and instances
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3
|
303
|
September 11, 2021
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[PSA] LLVM submodule URL change
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1
|
258
|
September 10, 2021
|
Calyx test failure
|
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2
|
204
|
September 10, 2021
|
SystemVerilog wire names
|
|
8
|
691
|
September 9, 2021
|
Verilog Emission docs
|
|
0
|
254
|
September 3, 2021
|
Target Triples for Hardware Compilers
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|
3
|
432
|
August 27, 2021
|
Calyx + CIRCT meeting
|
|
4
|
325
|
August 26, 2021
|
[FIRTOOL] automatic in always block
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3
|
276
|
August 24, 2021
|
`InstanceLike` and `ModuleLike` interfaces
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|
2
|
204
|
August 20, 2021
|
[FIRTOOL] Register Verilog emitter
|
|
3
|
236
|
August 18, 2021
|
[FYI] Windows builds on push to main
|
|
0
|
175
|
August 13, 2021
|
Comb MuxOp 2:1 vs N:1
|
|
18
|
383
|
August 11, 2021
|
New linker warnings during a build
|
|
11
|
1177
|
August 11, 2021
|
FIRRTL Dialect back to FIRRTL
|
|
6
|
662
|
July 29, 2021
|
[RFC] Unified CMake builds (for Python at least)
|
|
11
|
315
|
July 28, 2021
|
[RFC] Update C++ standard from 14 to 17
|
|
4
|
323
|
July 27, 2021
|
Proposal for Per-instance Metadata
|
|
6
|
477
|
July 27, 2021
|