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LLVM / Pull request discussion
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0
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249
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July 21, 2022
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Lack of constructs with a sensitivity list
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10
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270
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July 16, 2022
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FPGA development for a newbie?
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3
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497
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July 7, 2022
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[RFC] Representing pipelined loops
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31
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1218
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July 7, 2022
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Is there something like sv.logic instead of sv.reg/sv.wire?
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5
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438
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July 1, 2022
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ExportVerilog simplification for pretty-printing output verilog
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8
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335
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June 29, 2022
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[Comb][ExportVerilog] Add an operation to swap bits
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2
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201
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June 23, 2022
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[RFC] Stream Dialect
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21
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716
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June 23, 2022
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Build failed for CIRCT project
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5
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198
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June 13, 2022
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First results from using LLVM CIRCT on our design
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6
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499
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May 19, 2022
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Writing Custom FIRRTL Passes
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2
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311
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May 4, 2022
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Handshake: Circuit with optional result
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3
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207
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April 22, 2022
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Errors while running firtool, but Verilog still generated
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4
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326
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April 4, 2022
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Always_comb warning in Verilator
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0
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248
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April 2, 2022
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Verilog 93 output
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2
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180
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April 2, 2022
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Is there a way to generate Verilog stripped of non-synthesis code?
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7
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349
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April 1, 2022
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Is there a way to create a hash of synthesizable Verilog?
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1
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255
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March 31, 2022
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How are the Integration tests executed flow
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2
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209
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March 25, 2022
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Should "automatic logic" appear when firtool --verilog is specified?
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7
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215
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March 24, 2022
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One more error from Yosys
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0
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198
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March 24, 2022
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Longer .sv files from LLVM CIRCT than .v files from Chisel
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7
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254
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March 22, 2022
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How can I get firtool output into a folder?
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1
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150
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March 22, 2022
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CIRCT/MLIR dialect(s) for on-the-fly compiler generation for programmable heterogeneous (AI) accelerators?
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4
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461
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March 9, 2022
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Old ODM videos seem unavailable
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1
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163
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February 28, 2022
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LATTE '22 Announcement
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2
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369
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February 25, 2022
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FIRRTL to HW assertion error
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2
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239
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February 23, 2022
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Terminology: Instance
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2
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235
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February 10, 2022
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HIR vs Calyx
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4
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519
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February 4, 2022
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Joining the CIRCT Discord channel?
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2
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423
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January 13, 2022
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Reminder: Zoom link changed
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0
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202
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January 5, 2022
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