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Prototype Swift bindings for CIRCT are now open source!
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0
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290
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April 16, 2021
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Workshop on Language Technologies for Hardware Design
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0
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216
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April 8, 2021
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Conversion of FIRRTL CircuitOp
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3
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296
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April 8, 2021
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Calyx talk and next steps
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6
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631
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April 6, 2021
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Who gets email notifications about nightly build failures?
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4
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179
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March 29, 2021
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Python bindings discussion
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0
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225
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March 24, 2021
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[Moore] SV conversion to LLHD failed to run on LLHD-sim
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2
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237
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March 22, 2021
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CI failing with "llvm-lit: not found"
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11
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450
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March 16, 2021
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[RFC] Handshake top-level memory handling
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1
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200
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March 12, 2021
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HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description
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4
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601
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March 10, 2021
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Meetings to discuss onboarding / integration of external projects
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0
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211
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March 4, 2021
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[CFP] Languages, Tools, and Techniques for Accelerator Design
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0
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185
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February 23, 2021
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Expressing Verilog typedefs in MLIR
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3
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246
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February 21, 2021
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Missing LLHD symbol preventing updating MLIR
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1
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177
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February 10, 2021
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Conditional/ternary operator in RTL or SV?
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2
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237
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February 9, 2021
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Please use 'main' instead of 'master'
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2
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413
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February 8, 2021
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Representing device data
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11
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377
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February 7, 2021
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Weekly meeting videos
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0
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219
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January 27, 2021
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Proposal for DeMux ops and RSink ops in Handshake
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8
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195
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January 20, 2021
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[RFC] One-connect semantics for RTL
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2
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195
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January 15, 2021
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Support for floating/fixed/etc. types
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6
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205
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January 14, 2021
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HandshakeToFIRRTL verifications
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6
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202
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January 13, 2021
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Should `rtl.add i1, i1` return i1 or i2?
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9
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355
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January 10, 2021
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FIRRTL dialect rationale doc
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4
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324
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January 8, 2021
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Video from the talk today
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2
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322
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January 7, 2021
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SV/RTL dialect rationale
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2
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188
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January 7, 2021
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Clock and reset domains in the RTL dialect
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4
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187
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January 5, 2021
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Type Inference in RTL
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9
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341
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January 2, 2021
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Errors while building LLVM for CIRCT
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2
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195
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December 21, 2020
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Simulation test pipelines (non-Verilator)
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11
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643
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December 19, 2020
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