Let’s say we have a 32-bit architecture where 64-bit additions are done using 2 operations.
Instructions are defined as follow in TableGen:
defm ADD64 : ALU32<“add”, 1, 1, addc>;
defm ADD64C : ALU32<“addrc”, 1, 2, adde>;
Let’s assume that the carry bit is implicit and that the 2 operations must always be stuck together for the 64-bit add to work properly.
Is there a default guarantee that nothing will ever be inserted between “add” and “addrc” or is there a flag/condition to set somewhere to have that guarantee?
The register allocator expects to be able to insert spill code and copies between any instructions, except terminators.
The only way around that is to use pseudo-instructions that are expanded after RA.
If you model the effect of your carry on the instructions, the scheduler (and the other backend passes) should ensure that nothing that affects the carry will be inserted between your two instructions (assuming they are issued with nothing affecting the carry in between in the first place).
Therefore, you shouldn’t have to force them to be stuck together.
If you still do, what Jakob proposed is what you are looking for.
I really have to force them to stuck together otherwise the carry will just not work.
How about wrapping the 2 instructions in a bundle?
Would that be a way?
Using bundles here looks like a fragile way to handle that, IMHO.
Really, using a pseudo instruction seems the best approach for you.
For instance, you can match your add64 during isel with your pseudo instruction and expand it just before emitting the assembly file (add a pass using the hook: addPreEmitPass on your target).
If glue operands are used by the scheduler to keep instructions together, why can't the register allocator also do this?
Glue operands only exist during the instruction selection and early scheduling (SelectionDAG) phase of code generation. They're long gone by the time the MachineInstr scheduler or the register allocator sees your program. They're mostly used for ensuring that the early scheduler always generates a legal schedule, since it has a hard time modeling non-dataflow dependencies.
For the later phases of codegen, you need to either explicitly describe your dependencies (for example, having an explicit carry bit physical register that one instruction produces and the other consumes), or use the pseudo-instruction escape valve.
I agree. Take a look at the ARM backend instructions which operate on 2x32-bit registers as a 64 bit output. Look at things marked TwoOperandAliasConstraint in the tablegen files to see how they do this.