I’m trying to add a new DSP instruction to LLVM. In this instruction set, the last three bits of the instruction are designed to encode the functional unit. I read The LLVM target-Independent Code Generator and learned that VLIW Packetizer can map from instructions to functional units. So I read the source code for the Hexagon backend, but the coding in the Hexagon instruction set does not involve functional units. I want to ask for help, how to assign functional units to the last three bits of an instruction at instruction scheduling or at VLIW Packetizer? Or is there a similar back-end implementation that I can refer to?