Hello,
I find that the DwarfRegNum for riscv’s float point register starts from 32,
// Floating point registers
let RegAltNameIndices = [ABIRegAltName] in {
def F0_H : RISCVReg16<0, “f0”, [“ft0”]>, DwarfRegNum<[32]>;
def F1_H : RISCVReg16<1, “f1”, [“ft1”]>, DwarfRegNum<[33]>;
def F2_H : RISCVReg16<2, “f2”, [“ft2”]>, DwarfRegNum<[34]>;
def F3_H : RISCVReg16<3, “f3”, [“ft3”]>, DwarfRegNum<[35]>;
def F4_H : RISCVReg16<4, “f4”, [“ft4”]>, DwarfRegNum<[36]>;
def F5_H : RISCVReg16<5, “f5”, [“ft5”]>, DwarfRegNum<[37]>;
def F6_H : RISCVReg16<6, “f6”, [“ft6”]>, DwarfRegNum<[38]>;
def F7_H : RISCVReg16<7, “f7”, [“ft7”]>, DwarfRegNum<[39]>;
def F8_H : RISCVReg16<8, “f8”, [“fs0”]>, DwarfRegNum<[40]>;
def F9_H : RISCVReg16<9, “f9”, [“fs1”]>, DwarfRegNum<[41]>;
def F10_H : RISCVReg16<10,“f10”, [“fa0”]>, DwarfRegNum<[42]>;
But for GDB’s implementation, F0 starts from 33, and 32 is vacant. That leads to some errors when I trying to debug llvm compiled ELF with GDB.
/* RiscV register numbers. */
enum
{
RISCV_ZERO_REGNUM = 0, /* Read-only register, always 0. */
RISCV_RA_REGNUM = 1, /* Return Address. */
RISCV_SP_REGNUM = 2, /* Stack Pointer. */
RISCV_GP_REGNUM = 3, /* Global Pointer. */
RISCV_TP_REGNUM = 4, /* Thread Pointer. */
RISCV_FP_REGNUM = 8, /* Frame Pointer. */
RISCV_A0_REGNUM = 10, /* First argument. */
RISCV_A1_REGNUM = 11, /* Second argument. */
RISCV_A7_REGNUM = 17, /* Seventh argument. */
RISCV_PC_REGNUM = 32, /* Program Counter. */
RISCV_NUM_INTEGER_REGS = 32,
RISCV_FIRST_FP_REGNUM = 33, /* First Floating Point Register */
RISCV_FA0_REGNUM = 43,
RISCV_FA1_REGNUM = RISCV_FA0_REGNUM + 1,
RISCV_LAST_FP_REGNUM = 64, /* Last Floating Point Register */
RISCV_FIRST_CSR_REGNUM = 65, /* First CSR */
}