A question.

I found that LLVM were using Binutils to assemble the Assembly Code to the Machine Code, so I have a question, why LLVM don’t direct generate the machine code?

There was a protracted and rather uninteresting discussion of this matter on this list some months ago. I'll summarize the outcome of that thread briefly:

LLVM does generate machine code directly in the JIT.

For static compilation, no contributor has felt the need to eliminate the dependency on an external assembler. Why is this? First and foremost, an LLVM assembler would not materially advance the state of the art. At the same time, it would require significant platform-specific knowledge to author. It could easily constitute a considerable maintenance burden.

On Windows, where an assembler is not generally installed, a built-in assembler would be seen by some as a valuable component. However, when distributing a static compiler, bundling an assembler with it is a perfectly reasonable option. If GPL licensing is an issue, consult a lawyer. But I do observe that many closed-source compilers exist which use the system assembler, which is often gas.

There do exist partial implementations of direct machine code generators if you find this to be an area important enough to contribute. You can find them in lib/CodeGen/{ELF,MachO}Writer.cpp.

Please review the list archives if you want more detail.

-- Gordon

I have a question:
In the pattern below from X86

def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
      "inc{b}\tdst",
      [(set GR8:$dst, (add GR8:$src, 1))]>;

Since we are emitting only "inc $dst",
What makes sure that the $src and $dst are same register?

- Sanjiv

sanjiv gupta wrote:

I have a question:
In the pattern below from X86

def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
      "inc{b}\tdst",
      [(set GR8:$dst, (add GR8:$src, 1))]>;

Since we are emitting only "inc $dst",
What makes sure that the $src and $dst are same register?

- Sanjiv

It's enclosed inside :

let isTwoAddress = 1 in {
...
}

(you'll need to scroll up a fair amount to find this).

Richard

sanjiv gupta wrote:
> I have a question:
> In the pattern below from X86
>
> def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src),
> "inc{b}\tdst",
> [(set GR8:$dst, (add GR8:$src, 1))]>;
>
> Since we are emitting only "inc $dst",
> What makes sure that the $src and $dst are same register?
>
> - Sanjiv
It's enclosed inside :

let isTwoAddress = 1 in {
...
}

(you'll need to scroll up a fair amount to find this).

That means, it gets converted to
dst = src;
dst = dst + 1;

Right ?

- Sanjiv

sanjiv gupta wrote:

>>>
>> It's enclosed inside :
>>
>> let isTwoAddress = 1 in {
>> ...
>> }
>>
>> (you'll need to scroll up a fair amount to find this).
>>
>>
> That means, it gets converted to
> dst = src;
> dst = dst + 1;
>
> Right ?
>
> - Sanjiv
>
Yes, I believe the two address instruction pass performs exactly this
transformation.

Thanks.
How do I communicate if my CopyRegToReg instruction clobbers a register
of another register class? Is it through let Defs = [REG] { ... } while
defining the instr pattern?

- Sanjiv

BTW, please use the operand constraint syntax instead of the deprecated isTwoAddress syntax:

let Constraints = "$src1 = $dst" in

Evan

It's enclosed inside :

let isTwoAddress = 1 in {
...
}

(you'll need to scroll up a fair amount to find this).

That means, it gets converted to
dst = src;
dst = dst + 1;

Right ?

- Sanjiv

Yes, I believe the two address instruction pass performs exactly this
transformation.

Thanks.
How do I communicate if my CopyRegToReg instruction clobbers a register
of another register class? Is it through let Defs = [REG] { ... } while
defining the instr pattern?

That won't work. You don't know what physical registers are clobbered until you know the register assignments, right? One possibility is to add implicit defs when you create these instructions.

Evan

> How do I communicate if my CopyRegToReg instruction clobbers a
> register
> of another register class? Is it through let Defs = [REG] { ... }
> while
> defining the instr pattern?

That won't work. You don't know what physical registers are clobbered
until you know the register assignments, right? One possibility is to
add implicit defs when you create these instructions.

In our case that isn't a problem because we have only one register.