hi,
- For the following case in file llvm/test/CodeGen/AArch64/mul_pow2.ll
define i32 @mull6_sub(i32 %x) {
%mul = mul nsw i32 %x, 6
%sub = add nsw i32 %mul, -1
ret i32 %sub
}
- If I need generate following sequence, then I should put the const -1 into a register w9 as madd should not accept a const operator, so how to do?
mov w8, #6
mov w9, #-1
madd w0, w0, w8, w9
- For the const AddSub->getOperand(1), even when I use a ISD::ADD , it still retrun a const value
SDValue Const = DAG.getNode(ISD::ADD, DL, VT, AddSub->getOperand(1), DAG.getConstant(0, DL, VT));
(gdb) p Const->dump()
t5: i32 = Constant<-1>
$10 = void
(gdb) p AddSub->getOperand(1)->dump()
t5: i32 = Constant<-1>