About the additional implicit operands

In llvm, it will add additional implicit operands to use/def registers, so the number of operands for a MachineInstr will be more than the sum in MCInstrDesc.
But in function findFirstPredOperandIdx, it uses the return of MachineInstr::getNumOperands to index the MCID.OpInfo, without doubt this will be overflowed if instruction has no predicated operands and has additional implicit operands.
I don’t know what is the problem. We should not add additonal operand to a MachineInstr, or we can not call findFirstPredOperandIdx after a special pass?
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And there is a common case which will add additional implicit operands, def a subreg of the pair register:
$a0 = movi 1, implicit-def $s2a0
This implicit operand will be added after “Virtual Register Rewriter” pass.

I agree that MachineInstr::findFirstPredOperandIdx looks unsafe and it should be fixed. Maybe the loop should end at min(getNumOperands(), MCID.getNumOperands()).

Currently that function is only used by the ARM and R600 targets, so perhaps they know that there will be no implicit operands on their predicable instructions?

yeah, they use this function in a early pass, maybe in that time there are no additional implicit operands.