About the AMDGPU category

This category is for discussions specific to both the development of the AMDGPU target in upstream LLVM and its use inside the LLVM project and by outside compiler frontends (e.g. LLPC, Mesa).

It is not a forum for end-user support. (If helpful souls in the community answer such questions, then that’s awesome and welcome! However, AMD cannot offer support through this channel – we want expectations to be clear on this.)

Good topics for this category include:

  • High-level discussions about longer term and larger scope projects within the AMDGPU target, i.e. discussions that are too large in scope for an individual Phabricator review.
  • Questions and discussions about the semantics of target-specific intrinsics, address spaces, ABI, etc.
  • Questions about best practices for front-end code generation.

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does anybody know why amdgpu backend Drop the GCNRegBankReassign pass ?

as if we can resolve reg bank conflict, some stall cycle may not happen

@huoshanl, you should open a new post (in the AMDGPU category) for such a question instead of replying to an old, unrelated post.

Anyway, the GCNRegBankReassign pass was removed because nobody was able to come up with a case where it improves performance in practice. On the other hand, running this pass is pretty expensive and takes several percent of the overall compilation time. So, it was decided that it’s not worth running this pass and we should just remove it.

@Flakebi ,thanks for your reply.
in theory,resolve bank conflict can avoid some stall cycles per instruction。so it don’t understand why we can not get better performance with that pass.
follow nv programming guid, we can get better performance after ptxas resolve bank conflict.