accessing subwords in memory

I’m targeting a machine that can only load and store aligned 64-bit words,
but I’d like to be able to pack 8-, 16-, and 32-bit values into these words.
Loads will require various shifts and masks; stores are more complicated.
Does LLVM provide any support for such things?
Is there an example target I can look at for ideas?

Thanks,
Preston

I'm targeting a machine that can only load and store aligned 64-bit words,
but I'd like to be able to pack 8-, 16-, and 32-bit values into these words.
Loads will require various shifts and masks; stores are more complicated.
Does LLVM provide any support for such things?
Is there an example target I can look at for ideas?

The R600 subtarget in the AMDGPU backend does this with loads/stores for some
address spaces. See R600TargetLowering::lowerPrivateExtLoad()
and R600TargetLowering::lowerPrivateTruncStore().

-Tom

I'm targeting a machine that can only load and store aligned 64-bit words,

Does this imply that the target uses word addresses instead of byte addresses?

Boris

The machine uses byte addresses, but lacks instructions to do things like load/store byte.
So we must load a word, then find the desired byte.

Preston