ADDE to use branch registers


I am working on a LLVM backend that has eight different branch registers. I am having a lot of trouble with implementing the following instructions:

addcg $r0.1, $b0.0 = $r0.1, $r0.1, $b0.0

(r is a general purpose register and b is a 1 bit branch register) The branch register is used for carry in and carry out.

I have noticed that this instruction is very closely related to the ADDE instruction so this seemed like a logical place to start. I have seen that ADDC instructions and ADDE instructions are linked together using "glue". Is there a way to "save" the glue to one of the branch registers?

I have played around with some custom lowering of ADDC and ADDE instructions by trying to add an extra register to the instruction pattern. The following code snippet is not really working for me:

SDValue rvexTargetLowering::
LowerAddCG(SDValue Op, SelectionDAG &DAG) const
  unsigned Opc = Op.getOpcode();
  SDNode* N = Op.getNode();
  EVT VT = Op.getValueType();
  DebugLoc dl = N->getDebugLoc();

  SDValue BReg = DAG.getTargetConstant(rvex::B0, VT); // Add extra register to output

  return DAG.getNode(rvexISD::Addc, dl, VT, N->getOperand(0), N->getOperand(1), BReg);

Could anybody advice me on a way to make the backend know that the ADDE instruction will cause a branch register to be used?

Thanks in advance!

Maurice Daverveldt

Hi Maurice,

I had exactly the same problem, the last time i looked, i found that i could not use pattern matching to produce two solid results. I created the node, defining it to produce two results and take 3 args, and lowered it like so:

SDValue addcgRes = DAG.getNode(rvexISD::ADDCG, dl, DAG.getVTList(MVT::i32, MVT::i1),
                                                          arg0, arg1, arg2);

And then this can be manually handled in ISelDAGToDAG.

my backend uses the vex isa too, so if you wanna have a look its part of a driver i'm making:

please excuse the complete mess that it is though, i used it to learn llvm and haven't touched it for a while!