Adding instructions to MachineBlock

Hello,

I am writing a MachineFunction pass that converts vector instructions
to a sequence of scalar instructions. First, I go through the function
and look for vector registers. For each vector register, I create a
set of corresponding scalar registers using createVirtualRegister()
function and put it in a map. Then I go through the function and
replace vector instructions.The basic structure of the code is as
follows :

  for(MachineFunction::iterator BI=F.begin(), BE=F.end(); BI!=BE; ++BI) {
    MachineBasicBlock *BB = &*BI;

    std::vector<MachineInstr *> toRemove;
    std::vector<MachineInstr *> copies;

    for(MachineBasicBlock::iterator II=BB->begin(), IE=BB->end();
II!=IE; ++II) {
      MachineInstr *Instr = &*II;

      if(!isVectorInstr(Instr))
        continue;

      copies.clear();
      createCopies(F, Instr, copies);
      for(unsigned i=0, e=copies.size(); i!=e; ++i)
        BB->insert(II, copies[i]);
    }
    for(unsigned i=0, e=toRemove.size(); i!=e; ++i)
      BB->remove(toRemove[i]);
  }

The createCopies function creates a set of instructions. Say we have a
vector instruction vx <- f(vy, vz), and say the vector sizes of
vx,vy,vz are 2, then 'copies' will contain 2 instructions
x1<-f'(y1,z1) and x2<-f'(y2,z2), where f' is the corresponding scalar
instruction. Now, when I am trying to insert the new instructions into
the basic block (BB->insert(II, copies[i])), I am seeing a segfault.
MachineOperand::AddRegOperandToRegInfo is getting called by
BB->insert() and RegInfo->getRegUseDefListHead(getReg()) for the new
register is 0xffffffff somehow. I suspect I am not following some
rules when adding the instructions to a basic block. I would be
grateful if some one can point out what I am doing wrong, and provide
suggestions on how to go about doing this.

Thanks,
Manjunath

Why? That really isn't the level you want to be doing that sort of
thing normally. Usually, legalization turns illegal vector operations
into legal scalar operations.

-Eli

You are right, there are other approaches possible. In my case, I want
to retain some vector operations. So I translated all LLVM vector
instructions to machine vector instructions. Then I am writing this
phase to selectively translate some vector instructions to scalar
counter parts. But I feel the question is independent of this issue. I
am basically trying to add a new instruction with a def to a register.
BB->insert is failing because RegInfo->getRegUseDefListHead(getReg())
returns 0xffffffff.

Manjunath