Adding new vector instructions to LLVM Sparc backend

Hello all,

As a major degree project, I started working on adding vector instruction to the LLVM Sparc(modify for AJIT processor) backend.

My work is to implement VADDD, VSUBD, VUMULD, VSMULD instructions.

Their instruction format is as follows:-

31-30 op (always 10)

29-25 rd

24-19 op3

18-14 rs1

13 i (always 1)

12-10 (unused)

9-7 (datatype 8->001, 16->010, 32->100)

6-5 (always 10)

4-0 (rs2)

https://llvm.org/docs/ExtendingLLVM.html suggest me to use LLVM Custom Intrinsic to represent this VADDD operation. Is there any detail example code for other architectures available to look at?

Am I need to define a new class in SparcInsFormat.td because these instructions can’t use predefined format-3 class of other arithmetic instructions(8-bit felid of asi changed to specify vector datatype)?

Does the implementation of Sparc VIS resemble with these instructions?

May some LLVM backend experts give me an initial idea on what steps should I take to add these instructions?

I have gone through LLVM target-independent code generator documentation.

SPARC architecture manual and AJIT processor ISA is attached to the mail.

https://www.gaisler.com/doc/sparcv8.pdf

Thanks and Regards,
Shivam

isa.txt (11.4 KB)

Hi Shivam,

have a look at this talk: https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/

This shows how to add new instructions to LLVM.

Regards,
Kai