Adding scheduling constraints to intrinsics


I am working on fixing a bug in the x86 codegen and I need help in adding a new type of scheduling constraints.

The bug I am fixing is related to SSE instruction scheduling. SSE instructions use the “mxcsr” register for selecting the desired rounding mode. This control register is set/read by an intrinsic. Currently, this intrinsic has no scheduling deps and SSE instructions are scheduled freely before and after calls to this register. When working on this I noticed a case where an SSE instruction (after the intrinsic) was merged with a load instruction (before the intrinsic) during the isel phase. The merged SSE instruction was placed before the call to the intrinsic, producing an incorrect code.

In order to establish scheduling constraints, I declared a new phys register and wrapped the control intrinsic and SSE instructions with “Uses/Defs” definitions. My modifications did not add ‘blue edges’ to the scheduling graph. I also tried to change the intrinsic into a memory barrier, but it did not solve this case for obvious reasons.

My question is, how do I add these new scheduling constraints ?



Hi Nadav,

I haven't looked at SSE code, but it sounds like SD nodes for SSE instructions should have a chain operand to their control register write. The scheduler should have no problem with that.

The problem of isel merging load+SSE is independent of the scheduler of course. That match rule need to somehow respect or preserve the chain operand from SSE to control register.