While trying to get simulation with Verilator set up, to debug an FPGA failure, I ran into the warning below.
The FPGA works and has timing closure with Verilog from Chisel, but fails to get timing closure and also doesn’t work when I test it.
%Warning-LATCH: ALU.sv:144:3: Latch inferred for signal 'foo.unnamedblk1.unnamedblk2._GEN_3' (not all control paths of combinational always assign a value) : ... Suggest use of always_latch for intentional latches 144 | always_comb begin | ^~~~~~~~~~~
The case statement in question is fine, except that it has a default statement. My understanding of why this is a warning in Verilator, is that it is desirable to have every niggling little thing in Verilog explicit.
My point of view is not to get into right or wrong, but that it would make adoption easier if LLVM CIRCT could adhere to existing Verilog coding standards, whatever they might be.
casez (foo) 5'b00000: casez_tmp_4 = xxxx; [deleted] 5'b11110: casez_tmp_4 = bar; default: casez_tmp_4 = yyy; endcase end // always_comb
Another example of Verilog that “raises eyes” is to write(verilog pseudo code):
assign foo = (bar == 124)
rather than more explictly:
assign foo = (bar == 124) ? 1 : 0;