Hello LLVM developers,
I have a few questions regarding analysis and transformation of Machine IRs.
I am writing a scheduling pass that transforms single basic block loops. Details of the pass can be found in an email I sent two weeks ago.
I have changed my pass to run before Live Variable Analysis since then.
1, Induction variable recognition
I need to find which SSA value is used as the induction variable that controls a loop. Currently I determine that a value is the induction variable I am looking for if the following conditions are met:
- it is an operand of either the branch instruction or the instruction that sets the condition code for the branch
- the instruction that defines the value uses an operand defined by a phi instruction
- the phi instruction uses the value
For example, in the code below which loops n times,
(I0) v3 := n
(I1) v0 := 0
(I2) v1 := phi(v0, v2)
(I3) v2 := v1 + 1
(I4) cmp v2, v3
(I5) brne Loopbody
v2 is the induction variable because,
- v2 is an operand of I4
- I3 uses v1, which is defined by a phi instruction
- the phi instruction I2 uses v2
Is there a better way to do what I am trying to do?
Are there libraries I can use that work on Machine IRs?
- Insertion of add/sub instructions.
I need to change the number of times a loop is executed. In order to do that, I am considering modifying the value of the induction variable or the exit value before entering the loop. For example, if I wanted to execute the loop (n - 3) times in the code above, I could modify it in the following ways:
add 3 to v0
(I1) v0 :=
(I1_1) v0_1 := v0 + 3 <= add inserted here
(I2) v1 := phi(v0_1, v2) <= change operand
subtract 3 from v3.
(I0) v3 :=
(I0.a) v3_1 := v3 - 3 <= sub inserted here
(I4) cmp v2, v3_1 <= change operand
Is there a class or function that generates an add or sub instruction in a target-independent manner? I am looking for something similar to TargetInstrInfo::copyRegTpReg but one that creates other types of instructions.
Any advice, comments and suggestions are appreciated.
Thank you in advance.