Are Opcode and register mappings exposed anywhere?

I'm iterating over MCInsts and I'd like to examine particular instructions. For example, I'd like to look at all x86 CALL64m instructions. I may be missing something, but it seems like my only option is to use MCInstPrinter::getOpcodeName and compare strings. (Of course, I could iterate through the opcodes and build up a table of the ones I'm interested in to avoid string comparisons.)

Register mappings to names seem to be even worse. It appears you have to go through MCInstPrinter::printRegName(raw_ostream&, unsigned).

Is there a better way?

See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don’t know where it’s coming from. (Whether it’s a function or a member of a super class. Hopefully, if it’s a member, it’s public.)

PS Sorry for the duplicate, Stephen. I forgot to CC the list.

See the source here: https://github.com/earl/llvm-mirror/blob/master/lib/Target/X86/InstPrinter/X86IntelInstPrinter.cpp. It looks like getRegisterName might do what you want, but I don't know where it's coming from. (Whether it's a function or a member of a super class. Hopefully, if it's a member, it's public.)

Looks like X86ATTInstPrinter::getRegisterName() and X86IntelInstPrinter::getRegisterName() are static, public members. It would still be handy to expose an enum somewhere. This is to support something like:

if (Inst.getOpcode() == X86::CALL64r) {
  if (Inst.getOperand(0).getReg() == X86::RIP) {
    // ...
  }
}

E.g., exposing some of the tablegened enums in X86GenRegisterInfo.inc and X86GenInstrInfo.inc would be very handy.

Steve

Can’t you just include the generated files? What different way would you like them exposed?

It would be handy if they were installed along with the headers. Otherwise relying on them requires building LLVM and linking against that particular version of the libraries. That's all I meant by exposed.