ARM Intruction Constraint DestReg!=SrcReg patch?

Hi,

I am using a cross compiler to compiler for the arm5 architecture. For
this architecture it is not allowed that a destination register is also
used as source register.
In 2007 a patch was discussed at the mailing list, however my compiler
still is producing this result. Does anyone know if this patch is
actually applied?

* I use the following arguments:
llvm-gcc -mfpu=vfp -mlittle-endian -mfloat-abi=softfp -march=armv5 -S
-O3 foo.c -S -o foo.s
* Attached to this document foo.c and the resulting foo.s. Please, take
note of the illegal instruction mul r0, r0, r2 at line 18.
* The patch is discussed at:
http://www.mail-archive.com/llvm-commits@cs.uiuc.edu/msg14069.html
* llvm-gcc --version
llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)
Copyright (C) 2007 Free Software Foundation, Inc.

kind regards,
  Maarten Faddegon

foo.c (77 Bytes)

foo.s (567 Bytes)

Hi,

I am using a cross compiler to compiler for the arm5 architecture. For

this

architecture it is not allowed that a destination register is also used as

source

register.
In 2007 a patch was discussed at the mailing list, however my compiler

still is

producing this result. Does anyone know if this patch is actually applied?

* I use the following arguments:
llvm-gcc -mfpu=vfp -mlittle-endian -mfloat-abi=softfp -march=armv5 -S
-O3 foo.c -S -o foo.s
* Attached to this document foo.c and the resulting foo.s. Please, take

note of

the illegal instruction mul r0, r0, r2 at line 18.
* The patch is discussed at:
http://www.mail-archive.com/llvm-commits@cs.uiuc.edu/msg14069.html
* llvm-gcc --version
llvm-gcc (GCC) 4.2.1 (Based on Apple Inc. build 5658) (LLVM build)

Copyright

(C) 2007 Free Software Foundation, Inc.

If you read the Arm Architecture document for ARMv5, it states for MUL:

"Operand restriction: Specifying the same register for <Rd> and <Rm> was
previously described as producing UNPREDICTABLE results. There is no
restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5
implementations do not require this restriction either, because high
performance multipliers read all their operands prior to writing back any
results."

Therefore I do not believe you need to worry about this at all.

Hi,

Paul Curtis wrote:

If you read the Arm Architecture document for ARMv5, it states for MUL:

"Operand restriction: Specifying the same register for <Rd> and <Rm> was
previously described as producing UNPREDICTABLE results. There is no
restriction in ARMv6, and it is believed all relevant ARMv4 and ARMv5
implementations do not require this restriction either, because high
performance multipliers read all their operands prior to writing back any
results."

Therefore I do not believe you need to worry about this at all.

However, ARM support wrote:

The restriction on Rd == Rm was removed in ARMv6, but this was not a
retrospective change. That is, for ARMv4T and ARMv5TE the combination is
still officially unpredictable.

The comment in the ARM Architecture Reference Manual is intended as a
helpful note. However, in some ways it is unhelpful as there is still
no guarentee that a given implementation will support it.The
comment has since been removed from the latest edition.

The advise would be to assume that restriction still applies to ARMv4T or
ARMv5TE when developing portable code

Thus, if I want to follow this advice, is there a way to force LLVM to
not output instructions such as "mul r0, r0, r2"? As I believe was the
effect of the Lauro Ramos Venancio's patch.

kind regards,
  Maarten Faddegon

Thus, if I want to follow this advice, is there a way to force LLVM to
not output instructions such as "mul r0, r0, r2"? As I believe was the
effect of the Lauro Ramos Venancio's patch.

The patch was neither complete nor applied to mainline. So, right now
there is no way.

If you're fine with using the PBQP register allocator, it would be very
simple to extend the PBQP formulation with a constraint that prohibits
allocating the result and one of the source operands to the same register.