ARM TargetLowering broken?

everyone--

My build of LLVM-GCC from top-of-trunk sources is failing with the assertion in ARMISelTargetLowering at line 667, in LowerRET, where it says "Do not know how to return this many arguments!" This happens when the cross-compiler attempts to build _muldc3 for libgcc2.

The more I have investigated this problem, them more convinced I have become that this isn't a stupid newbie bug, but something more troubling in the integration of ARM code generation with LLVM-GCC.

For reasons I haven't been able to understand yet, there are nine operands to the ISD::RET node when this happens, which has me a little confused because _muldc3 is not really a very complex function (please pardon the pun). It has one return point, where it returns a CTYPE value, which I'm expecting is a represented internally as a pair of floating point numbers.

What's the more likely explanation for the error I'm seeing?

+ The ARM TargetLowering code for ISD::RET is busted for GCC's complex number types.

+ The LLVM backed in GCC is busted for complex types.

I don't know, but I suspect the former. I'm still grinding on this problem in my copious spare time, and I'll be grateful for any tips from LLVM experts that come my way. My next step: try to coax my LLVM-GCC variant to emit the LLVM IR for what it's doing when it compiles _muldc3 in libgcc2.

If you've read this far, then thank you for your attention.

My build of LLVM-GCC from top-of-trunk sources is failing with the

assertion in ARMISelTargetLowering at line 667, in LowerRET, where it

says “Do not know how to return this many arguments!” This happens

when the cross-compiler attempts to build _muldc3 for libgcc2.

The good news (for me) is that…

#define ARM_ABI_DEFAULT ARM_ABI_AAPCS

…makes this problem go away.

Why? Because, without it, the LLVM-GCC code generator seems to want to bitcast the CDType complex number structure into an i128 return value, and the ARM target in LLVM doesn’t like that at all. It turns out that neither do most of the other targets. The only target that doesn’t seem to complain about this is the x86-64 target. Too bad I don’t have x86-64 hardware to play with…

In any case, it looks like either A) the ARM backend, as well as the MIPS and PowerPC backends, could use to be improved to support lowering i128 return values in the ISD::RET nodes into instructions that makes sense, or B) the LLVM-GCC code generator ought not to be generating returns for data types that the underlying target architecture doesn’t like. I’d try to tackle the former approach, but I’d probably make a hash of it because I’m a total noob. I’m not sure I think the latter approach is the right choice. So, I’m just going to drop this problem and move on to the next interesting thing.

There’s nothing about any of this in $LLVM/lib/Target/ARM/README.txt, and that made me a little sad. I would have liked to see something in there about it, and I would write something there myself, except I can’t. This kvetch here will have to do.

If you’ve read this far, then thank you for your attention.

I now have a toolchain building for my crazy new ARM target that doesn’t really exist yet. If you have questions about anything above, please ask on the list.