ARMSchedule.td MipsSchedule.td etc.

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#1

I apologize if this has been asked before but which classes utilize the information in these files? I am asking since I am trying to extend the MIPS backend to 64bit among other things.

Thanks in advance,

Carter.

#2

Actually after some digging I managed to answer these questions for myself. I am guessing that this information is used by the Schedule* classes in CodeGen.

#3

Yes. But it is not really being used by most (any?) targets because post-RA scheduling is disabled by default. Also, the existing model is very limited in what types of micro-architectures can be described. I've been extending it to enable scheduling of multi-issue targets, targets with overlapping FU usage, and targets that use and define registers in multiple pipeline stages.

See /include/llvm/Target/TargetInstrItineraries.h for some information. The CortexA8Itineraries description in ARMScheduleV7.td is where I am using these new features to model the Cortex-A8. All of this is a work in progress...

I suppose when I finish I will write up something describing the new Itinerary model and how to use it...

David

#4

Thanks. I guess I will ignore it for now. It seems like the current Mips experimental backend doesnt even have this information hooked into the target machine.