Assembly Printer

I am trying to understand how LLVM does code generation and I have a couple of questions.
I am using LLVM 2.6.

First,
if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right?
Using Sparc as an example, if I wanted to output “mysra” instead of “sra”, in SparcInstrInfo.td, I would write,

defm SRA : F3_12<“mysra”, 0b100111, sra>;

Is this correct?
When I run llc with option -march=sparc, after I make the modification, it still outputs “sra”, not “mysra”. I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes “mysra”. However, when I run gdb and do “print AsmStrs + (Bits & 1023)”, it prints “sra”.
Does this make sense or am I just overlooking something?

The second question is about pattern matching of instructions.
I found that some of the target instructions do not have corresponding patterns to match.
For example, in SparcInstrInfo.td, “udiv” and “sdiv” don’t seem to have any patterns specified.

defm UDIV : F3_12np<“udiv”, 0b001110>;
defm SDIV : F3_12np<“sdiv”, 0b001111>;

Is this because these instructions are handled differently from other instructions in SparcISelDAGToDAG.cpp?
In function SparcDAGToDAGISel::Select(SDValue Op), instruction selection for “sdiv” and “udiv” is done in the switch-case statement, while SelectCode(Op) takes care of the other instructions**.**

Thank you…

I am trying to understand how LLVM does code generation and I have a couple of questions.
I am using LLVM 2.6.

First,
if I want to change the name of an instruction, all I need to do is to modify the XXXInstrInfo.td, right?
Using Sparc as an example, if I wanted to output “mysra” instead of “sra”, in SparcInstrInfo.td, I would write,

defm SRA : F3_12<“mysra”, 0b100111, sra>;

Is this correct?

Yes.

When I run llc with option -march=sparc, after I make the modification, it still outputs “sra”, not “mysra”. I looked into SparcGenAsmWriter.inc, and made sure that string AsmStrs includes “mysra”. However, when I run gdb and do “print AsmStrs + (Bits & 1023)”, it prints “sra”.
Does this make sense or am I just overlooking something?

Sounds like something is being overlooked. Perhaps tblgen didn’t get rerun or something didn’t get relinked.

The second question is about pattern matching of instructions.
I found that some of the target instructions do not have corresponding patterns to match.
For example, in SparcInstrInfo.td, “udiv” and “sdiv” don’t seem to have any patterns specified.

defm UDIV : F3_12np<“udiv”, 0b001110>;
defm SDIV : F3_12np<“sdiv”, 0b001111>;

Is this because these instructions are handled differently from other instructions in SparcISelDAGToDAG.cpp?
In function SparcDAGToDAGISel::Select(SDValue Op), instruction selection for “sdiv” and “udiv” is done in the switch-case statement, while SelectCode(Op) takes care of the other instructions**.**

Yep, exactly,

-Chris

IMHO, this is a poor way to do this kind of thing. It eventually
leads to confusion where someone things SRA means "sra" and someone
else thinks it meas "mysra." It gets worse as "mysra" acquires
subtly different semantics than "sra." Better to write a separate pattern
and use AddedComplexity to prefer it.

Just a nugget of wisdom from personal experience. :slight_smile:

                            -Dave

Hello.

Thank you for your advice.

I am still trying to understand how code generation works and see how the changes I made in the .td files affect the output. I have managed to see the names of the instructions change in the output (it turns out it was a linkage problem), and right now I am trying to figure out how function call lowering works. If I get to the point where I can start implementing a real backend, I will certainly change the definition and everything else.