Assert in register allocation during last chance recoloring

Hi,

I opened the bug #31122 for this issue.

There are two parts to this problem. Compiled using “llc -debug-only=regalloc test.ll”, the test case attached to the bug fails with

VirtRegMap.h:119: void llvm::VirtRegMap::clearVirt(unsigned int): Assertion `Virt2PhysMap[virtReg] != NO_PHYS_REG && “attempt to clear a not assigned virtual register”’ failed.

The code looks like:

%vreg647 = COPY %vreg645; QQQQPR_with_dsub_7_then_ssub_0:%vreg647 QQQQPR:%vreg645

%vreg657 = COPY %vreg655; QQQQPR_with_dsub_7_then_ssub_0:%vreg657 QQQQPR:%vreg655

%vreg679 = COPY %vreg678; QPR_VFP2:%vreg679 QPR:%vreg678

%vreg657:dsub_7_then_ssub_0 = VDIVS %vreg679:ssub_2, %vreg647:dsub_7_then_ssub_0, pred:14, pred:%noreg; QQQQPR_with_dsub_7_then_ssub_0:%vreg657,%vreg647 QPR_VFP2:%vreg679

%vreg659 = COPY %vreg657; QQQQPR:%vreg659 QQQQPR_with_dsub_7_then_ssub_0:%vreg657

This problem occurs during last chance recoloring, where %vreg679 doesn’t get allocated (and is marked as not spillable), so last chance recoloring kicks in. It tries to allocate Q0 to %vreg679, where Q0_Q1_Q2_Q3 is assigned to %vreg647, which interferes with %vreg679. Upon trying to allocate a register to %vreg647, %vreg679 gets evicted from Q0. But %vreg679 is a fixed register, so it shouldn’t get evicted. Recoloring is thus deemed successful, and upon returning from tryRecoloringCandidates, we assert when trying to unassign %vreg679.

I can get around this by moving the virtual register under consideration in tryLastChanceRecoloring (%vreg679) to RS_Done stage right before the call to tryRecolringCandidates, and then restoring the original stage afterward. This prevents the eviction of %vreg679 during recoloring. Alternatively, I can check FixedRegisters in canEvictInterference and return false.

After the assert is gone, I run into “LLVM ERROR: ran out of registers during register allocation”. Increasing lcr-max-depth doesn’t help.

To get past this error, I am thinking about spilling an actual physical register if last chance recoloring fails. For example,

P = ….

virtX = …. Last chance recoloring fails,

… = P

…. = virtX

will result in something along the lines of

P = ….

spill P to fi#0 (original P)

P = …. (virtX is now in P)

….

Spill P to fi#1 (this is virtX)

Reload P form from fi#0 (original P)

… = P

….

Reload P from fi#1 (this is virtX)

= P

Does anyone have any other suggestions about dealing with this problem?

Thank you,

Sanjin

Hi Sanjin,

The spilling/spliting strategy for big registers is known to be weak so I am not surprised you run into this problem.

I’ll have a closer look (sometime this week or next week) and I’ll comment in the PR.

Cheers,
-Quentin