Assert in TargetLoweringBase.cpp

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1

This post is related to the following post http://lists.llvm.org/pipermail/llvm-dev/2016-April/098823.html

I’m still trying to compile a library with clang. But now I’m getting as assert in

lib/CodeGen/TargetLoweringBase.cpp:1155: virtual llvm::EVT llvm::TargetLoweringBase::getSetCCResultType(llvm::LLVMContext&, llvm::EVT) const: Assertion `!VT.isVector() && “No default SetCC type for vectors!”’ failed.

I’m still learning LLVM, but unfortunately I don’t know what this assert could be related to. I would really appreciate any input on this.

I’m running clang-3.5. For now I’m stuck with this version. If you need output with -debug option I can certainly provide it.

Any help is appreciated.

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Hello.
     I want to implement vector comparison in my SIMD processor back end.

     To test this I try to compile the following LLVM program:
       define i1 @foo(i64* %A, i64* %B, i1* %C, i64 %N) #0 {
         entry:
           %0 = getelementptr inbounds i64, i64* %A, i64 0
           %1 = bitcast i64* %0 to <8 x i64>*
           %wide.load = load <8 x i64>, <8 x i64>* %1, align 4
           %2 = getelementptr inbounds i64, i64* %B, i64 0
           %3 = bitcast i64* %2 to <8 x i64>*
           %wide.load17 = load <8 x i64>, <8 x i64>* %3, align 4
           %4 = icmp eq <8 x i64> %wide.load17, %wide.load
           %5 = getelementptr inbounds i1, i1* %C, i64 0
           %6 = bitcast i1* %5 to <8 x i1>*
           store <8 x i1> %4, <8 x i1>* %6, align 4
           %res = load i1, i1* %C, align 4
           ret i1 %res
       }
     But, I get with llc the following error when compiling the LLVM program:
  Legally typed node: t18: v8i64,ch = load<LD64[%3](align=4)> t0, t4, undef:i64
  Promote integer result: t20: v8i1 = setcc t18, t17, seteq:ch
         llc: /llvm38Nov2016/llvm/lib/CodeGen/TargetLoweringBase.cpp:1399: virtual llvm::EVT llvm::TargetLoweringBase::getSetCCResultType(const llvm::DataLayout&, llvm::LLVMContext&, llvm::EVT) const: Assertion `!VT.isVector() && "No default SetCC type for vectors!"' failed.
     (I can provide a complete -debug output of llc, or I guess even the back end source code.)
     (Another thread on llvm-dev reported this error, but no solution was provided: Redirecting to Google Groups .)

     Just to give more details about my implementation of vector SETCC in the back end: as usual, I got inspired from the Mips LLVM back end - the MSA SIMD subset. From lib/Target/Mips/MipsMSAInstrInfo.td I copied most definitions and classes containing the "vset" string in them, and also JUST ONE vsplat record:
     def vseteq_v8i64 : vsetcc_type<v8i64, SETEQ>;
     def vsetle_v8i64 : vsetcc_type<v8i64, SETLE>;
     ...
     def vsplati16 : PatFrag<(ops node:$e0),
                         (v8i16 (build_vector node:$e0, node:$e0,
                                              node:$e0, node:$e0,
                                              node:$e0, node:$e0))>;

     Also, I wrote in MyConnexISelLowering.cpp:
       SDValue ConnexTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
         ...
         case ISD::EXTRACT_VECTOR_ELT:
           // From [LLVM]/llvm/lib/Target/Mips/MipsSEISelLowering.cpp
           return LowerEXTRACT_VECTOR_ELT(Op, DAG);
         ...
       }

       SDValue ConnexTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
                                                     SelectionDAG &DAG) const {

        return SDValue();
       }

     Could you please tell me if you have any idea with what might be wrong?

   Thank you,
     Alex

3

You need to implement getSetCCResultType. I’m not sure why the default doesn’t do anything to handle them. You might want it to return an vector for example

-Matt

4

Hello.
     Matt, sorry for the late reply. I finally made it work somewhat.

     Basically I copy-pasted the method from another back end, llvm/lib/Target/NVPTX/NVPTXISelLowering.h (using the similar method from the Mips back end didn't work):
     EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
                            EVT VT) const { //override {
       if (VT.isVector())
         return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
        return MVT::i1;
     }

    Please let me know if you see issues here.

   Now, for the LLVM program mentioned in the previous email
(prefix ASM instruction notation) it lowers correctly the setcc corresponding to LLVM's icmp instruction. But now I have issues in a different part - I'll come back on this.

   Thank you,
     Alex