AVX-512 foldable instructions Pattern Matching VMOVDQU32Zm

Hello,

I am trying to understand the vectorized llvm instruction selection (pattern matching). there i found how
store<ST64bitcast (i32* getelementptr inbounds ([34 x i32], [34 x i32]* @a, i64 0, i64 16) to <16 x i32>*)(tbaa=<0x2c96d88>)> is mapped to

VMOVDQU32Zmr<Mem:ST64bitcast (i32* getelementptr inbounds ([34 x i32], [34 x i32]* @a, i64 0, i64 16) to <16 x i32>*)(tbaa=<0x2c96d88>)> Register:i64 %RIP, TargetConstant:i8<1>, Register:i64 %noreg, TargetGlobalAddress:i32<[34 x i32]* @a> + 64, Register:i32 %noreg, t16, t18

but when i searched VMOVDQU32Zm instruction i didnt find its definition in .td file rather its mentioned in x86instrinfo.cpp still not defined rather it says AVX-512 foldable instructions
it is just called via .inc file.

{ X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },

Please clarify the concept of pattern matching for such instructions. what are foldable instructions?

Thank You

Look for "defm VMOVDQU32". See also http://llvm.org/docs/TableGen/LangIntro.html#multiclass-definitions-and-instances

-Eli