Backend for the ZPU - a stack based / zero operand CPU

We mean ZPU looks like x86 fp stack. We handle it by register
allocating it like a normal register based cpu than add a x87
stackifer pass to convert it to stack operations.


You do not have to. Take a look at PPC and ARM branch fix up passes.
llvm backends compute exact length of instructions so it can determine
when it is necessary to convert a conditional branch to a conditional
branch of the opposite condition and a unconditional branch.

Branches are only part of the problem, they could have been handled
at the assembler level pretty much.

The ZPU has variable length instructions that have to be calculated link


   poppcrel N ; jump to PC relative address

The location of N(a global variable) relative affects the length of
the "poppcrel N"

The above could be anything from a 2 byte to a 6 byte instruction.

This is all done in the gas + linker today in a close to optimal fashion.
It is conceivable to write something that would move around on functions
to make pc relative references a small as possible globally. Seems a
bit over the top for probably miniscule gains. :slight_smile:

As long as I can use gas + link unchanged, I'd be happy to leave
that tested code as-is, there is nothing more interesting to be done
with it.