I was trying to create an LLVM backend for a processor with a very simple architecture and that does all instructions like load, store, arithmetic and logical instructions using a bunch of majority functions. The processor has only one instruction(majority function) in its ISA and breaks down all other instructions into a number of majority instructions depending on what instruction it is. All the instructions have different combinations of majority operations. Is there any way to implement this without creating a new Selection DAG node for the majority operation? Also can i create a selection DAG node in the backend instruction info itself? If so then how?
I was thinking of creation of a new Selection DAG node and mapping all the other instructions like loads, stores as pseudo instructions and breaking them up. Can someone please help me with this?
Why don’t you just write TableGen patterns to match the various selection-DAG nodes onto the correct combinations of your instruction? -Hal
The architecture just supports one instruction which could be actually written down as ORs and ANDs and but there is no particular DAG node that it can directly map onto. Is there a way to describe that instruction ? Like if the instruction does the AB+BC+CA(if A, B,C are operands) can this be written somehow in tablegen pattern?
I don’t see why not. You can write a TableGen definition for the instruction, which does not need to correspond directly to some SDAG node (many instructions don’t) and then you can map SDAG nodes onto combinations of your instruction using other patterns. For example, something like this: def : Pat <(i1 (selectcc i1:$lhs, i1:$rhs, i1:$tval, i1:$fval, SETLT)), (CROR (CRAND (CRANDC $lhs, $rhs), $tval), (CRAND (CRORC $rhs, $lhs), $fval))>; you’ll find lots of examples in lib/Target/PowerPC/PPCInstrInfo.td and other backends. -Hal