backend question

Hello,

I’m just starting to work on a backend for a custom cpu. For some instructions this cpu has two flavors: first performs an operation, and the second performs an operation and updates condition codes (carry, zero, overflow, negative etc) based on the outcome. For example: add rd,rs instruction adds the contents of register rs to register rd and places the result in rd; add.cc rd, rs does the same and updates the condition codes. Can anybody point out an example of how such instructions should be defined in a corresponding xxInstrInfo.td file please?

Sincerely,
– Lev.

ARM has similar instruction pairs, look at ADD/ADDS, SUB/SUBS in ARMInstrInfo.td

/jakob

Thank you very very much for your answer!

Am I correct in my understanding that “let Defs = [CPSR]” in the definition of AI1_bin_s_irs multiclass explains the effect of setting conditional codes to the TableGen in ARM’s case?

Sincerely,
– Lev.

Yes, that tells the instruction selector and scheduler that the CPSR register is clobbered by this instruction.