[backend]two-address encoding in llvm tblgen

Dear there,

I'm developing an instruction layout like:

opcode | rd| ts

and its semantics is:

rd= rd opcode rs

But when I describe it in td file like this:

class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
  bits<5> rd;
  bits<6> rs;
  let Opcode=Op;
}

It complains for 'rd'. I was wondering if there is any standard way of
doing this?

Thanks,
Xiaochu

From: "Xiaochu Liu via llvm-dev" <llvm-dev@lists.llvm.org>
To: "LLVM Developers Mailing List" <llvm-dev@lists.llvm.org>
Sent: Tuesday, November 24, 2015 5:08:49 PM
Subject: [llvm-dev] [backend]two-address encoding in llvm tblgen

Dear there,

I'm developing an instruction layout like:

opcode | rd| ts

and its semantics is:

rd= rd opcode rs

But when I describe it in td file like this:

class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rd, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
  bits<5> rd;
  bits<6> rs;
  let Opcode=Op;
}

You need to use a different input and output register, and then tie them together:

class R<bits<5> Op, string OpcodeStr, list<dag> Pattern>
: InstV<(outs GPR:$rd), (ins GPR:$rdi, GPR:$rs), !strconcat(OpcodeStr,
"\t$rd, $rs"), Pattern> {
  bits<5> rd;
  bits<6> rs;
  let Opcode=Op;

  let Constraints = "$rdi = $rd";
  let DisableEncoding = "$rdi";
}

-Hal

Hi Hal,

Thanks for your reply and it is helpful!

I have a quick question:
When I use BuildMI to build instructions in this case, do I have to
add all three of the register operands explicitly (operand 0 and 1 are
the same)?

Thanks,
Xiaochu

From: "Xiaochu Liu" <xiaochu1122@gmail.com>
To: "Hal Finkel" <hfinkel@anl.gov>
Cc: "LLVM Developers Mailing List" <llvm-dev@lists.llvm.org>
Sent: Tuesday, November 24, 2015 5:35:36 PM
Subject: Re: [llvm-dev] [backend]two-address encoding in llvm tblgen

Hi Hal,

Thanks for your reply and it is helpful!

I have a quick question:
When I use BuildMI to build instructions in this case, do I have to
add all three of the register operands explicitly (operand 0 and 1
are
the same)?

Yes, you'll need to add all three operands. Note that before register allocations (specifically, when the MIs are still in SSA form), they'll have different virtual registers.

-Hal

Thank you so much!