best way to implement complex addressing modes

The ARM has some very powerful and complex addressing modes. For
example, the data processing instructions (and, orr, add, ..) have an
addressing mode that has 11 options (imm, reg, and 9 reg + some
shift).

I am considering 3 ways to implement this:

1) define one instruction that has an ARM specific addressing mode
that covers all 11 possibilities.
2) define 11 instructions.
3) a mix of the two

I believe that implementation 1 would be the most elegant one. It
would have a one to one correspondence with the ARM Architecture
Reference Model.

For two to work it would be necessary to write custom select code to
use the more uncommon addressing options.

For three I could use the multiclass feature to implement add_ri and
add_rr. The add_ri instruction would use a custom addressing mode for
the second operand.

Currently I am planning to implement 3 because it looks like to be the
easiest to implement.

Any comments?

Thanks,
Rafael

I'm not sure exactly what the constraints you have are, but I'd suggest using a 'complexpattern' to match these, along with some custom C++ code to do the actual matching. This mechanism works well for real addressing modes, but can also work for generic other things as well. If you have specific questions, please ask. Also, don't be afraid to experiment and try different approaches, sometimes the best way to appreciate a good solution is to learn what's terrible about the bad ones :slight_smile:

-Chris

Hi Chris,

> The ARM has some very powerful and complex addressing modes. For
> example, the data processing instructions (and, orr, add, ..) have
> an addressing mode that has 11 options (imm, reg, and 9 reg + some
> shift).

I'm not sure exactly what the constraints you have are

For those interested, here's the kind of things you could do, at least
on older ARM architectures.

    # Jump-table dispatch.
    cmp r0, #42
    addls pc, pc, r0, lsl #2

    # Load first byte of 8-byte element from array at r1 indexed by r2.
    ldrb r0, [r1, r2, lsl #3]

I'd have thought PowerPC has some similarities?

Cheers,

Ralph.

PPC just has R+R and R+I addressing modes. X86 has other crazy things that can fold shifts 3 adds and other stuff into the addressing mode. See lib/Target/X86/X86ISelDAGToDAG.cpp:SelectAddr to see it's implementation in llvm.

-Chris