Hello everyone,
I'm still new to llvm and therefore wonder if there's a shorter way for
the following situation, see attached td-file:
My processor has a FPU where both operands can read from a register or
from memory, and the result can be stored in a register or in memory. I
defined two cases (output to register _r and to memory _m) in a
multiclass. But I had to repeat similar code four times for the four
possible operand combinations.
I'd like to define the two possibilities for each operand independently,
i.e. e.g. for Ty:$srca and (load LoadRegs:$ptra), and automatically
generate all combinations. Is this possible?
Thanks for any advice!
Best regards,
Markus
InstrInfoFragment.td (2.47 KB)