BoF: Co-ordinating RISC-V development in LLVM, AND RISC-V LLVM working session event

There will be a RISC-V focused Birds of a Feather (BoF) session at the LLVM
Dev Meeting in a few weeks time
(Wednesday, October 18, 4:20pm - 5:05pm)
The aim of this session is to bring together everyone with an interest in
RISC-V support LLVM, and especially those from companies who have had private
out-of-tree development forks and work on how best to move development
forwards as a group effort.

On the day before the Dev Meeting (Tuesday October 17th), I'm organising a
longer working session. This will be held at a Qualcomm location in San Jose,
between approximately 10am-4pm. Anyone interested in contributing to RISC-V
support in LLVM projects is incredibly welcome. Food and refreshments will be
provided. Please email me at to confirm attendance. I
appreciate that the scheduling may not work for those travelling to the Bay
Area just for the Dev Meeting. I've assumed that Tue 17th is likely to be no
more likely to be unworkable than the Fri the 20th, but do let me know if you
think I'm wrong about that. This session will be implementation focused (i.e.
hacking, white-boarding).

I hope the BoF will provide a good venue for discussion and planning. I've
pasted the proposed session details below for reference - please respond to
this thread if you have more thoughts on what you would like to discuss. For
further background, you might find this recent blog post useful

RISC-V is a free and open instruction set architecture that has seen rapidly
growing interest and adoption over the past couple of years. RISC-V Foundation
members include AMD, Google, NVIDIA, NXP, Qualcomm, Samsung, and many more.
Many RISC-V adopters, developers, and users are keen to see RISC-V support in
their favourite compiler toolchain. This birds of a feather session aims to
bring together all interested parties and better co-ordinate development
effort - turning that interest in to high quality patches. Issues for
discussion include:

* How best to co-ordinate development, minimising duplicated effort and
  bringing RISC-V to a top-tier architecture as quickly as possible
* How to test and support the huge number of possible RISC-V ISA variants
  (official extensions, as well as custom instructions).
* Support for variable-length vectors in the proposed RISC-V vector extension,
  and opportunities for LLVM developers to feed in to the ISA definition
* Ways for companies who currently use a auto-generated RISC-V LLVM backend to
  move to building upon and contributing to the upstream codebase

UPDATE: after feedback from several groups, this will now be on
__Friday 20th Oct__ (i.e. the day after the LLVM Dev Meeting
finishes). As before, please email me at to confirm