Can' get coupled ADDSUB instruction in assembler code

MLIR
#1

Hello!
There are such code fragments in my MLIR code:

Value in1addin2 = builder.create<Arith::AddFOp>(loc, in1, in2);
Value in1subin2 = builder.create<Arith::SubFOp>(loc, in1, in2);

After this MLIR code has been lowered down to LLVM and then translated into X86-ASM instructions, the above-mentioned operation pares AddFOp/SubFOp turn into the following ASM code snippets:

14272d: c4 c1 1c 5c da              vsubps    %ymm10, %ymm12, %ymm3
142732: c5 d4 58 f0                 vaddps    %ymm0, %ymm5, %ymm6
142736: c5 fc 5c c5                 vsubps     %ymm5, %ymm0, %ymm0
14273a: c5 a4 58 ef                 vaddps    %ymm7, %ymm11, %ymm5

But, you know, X86 (and other CPUs) instruction set contains coupled ADD/SUB vector instructions. How can I get single vaddsubps instruction in code instead of vaddps/vsubps couple?
Is it possible to insert such an operation (coupled ADD/SUB) into X86Vector or Arith dialect with the support of appropriate coupled ADD/SUB LLVM instruction?

#2

What is the types of in1 and in2, and what is the llvm optimization pipeline that you use?

#3

Both in1 and in2 are f32 memref elements, and passes ConvertVectorToLLVM and ConvertMathToLLVM are used to get final LLVM IR

#4

Is there anybody who can suggest how to overcome this problem?

#5

You haven’t said what your LLVM optimization pipeline is. That is, post generating LLVM IR what LLVM passes do you run and in which order, that (e.g., 45015 – [X86][AVX] Failure to generate vaddsubps for pattern after 19b62b79) and what your backend cost model in LLVM dictates this op as we don’t have a direct mapping to it here AFAICS. With the IR generated it becomes an LLVM question as far as I can see, where setting the correct tripple, using VectorCombine (or what not) pass and having vectors or profitable length would all affect this.