Can LLVM CIRCT output negedge async reset?

Incubator CIRCT
1

Near as I can tell, Chisel FIRRTL can’t generate negedge async reset directly:

https://groups.google.com/g/chisel-users/c/Q1jgdcnIf6w

Can LLVM CIRCT articulate negedge async reset in MLIR and output the Verilog?

always @(posedge clock or negedge reset) begin
if (!reset) begin

2

Yes, CIRCT can represent this and emit the Verilog you are looking for:

hw.module @example(%clock: i1, %reset: i1) {
  sv.always posedge %clock, negedge %reset {
    %allOnes = hw.constant true
    %resetn = comb.xor %reset, %allOnes : i1
    sv.if %resetn {

    }
  }
}

This is emitted as:

module example(                                                                                                                                                                                                                                               
  input clock,                                                                                                                                                                                                                                            
        reset                                                                                                                                                                                                                             
);                                                                                                                                                                                                                                                                              
                                                                                                                                                                                                                                                                                
  always @(posedge clock or negedge reset) begin                                                                                                                                                                                 
    if (~reset) begin                                                                                                                                                                                                   
    end                                                                                                                                                                                                                                                                         
  end // always @(posedge, negedge)                                                                                                                                                                                                                                             
endmodule

But as far as Chisel and FIRRTL go, I do not think there is any support today that can actually target these constructs.

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