I used to think circt is a project which can take some high-level language as input , .fir .c etc. and then lower them into verilog finally, but I noticed that circt currently has a new dialect ‘llhd’ and given my preceded research, llhd can generate netlist on end.
so, can we use circt to generate netlist instead of just verilog rtl level code?
What form of netlist are you interested in?
I’m sorry about that I proposed a stupid question It seems that llhd use the outside synthesis tool to generate the synthesized netlists and they represent the synthesized netlists with llhd ir, that is magic for me and I still need to keep studying more about their process.
Actually any forms of netlist is ok, netlist is just a description level of circuit and we can describe it in form of verilog, but mostly in form of BLIF、AIG.
Currently, each design automation tool lowers HDLs to its own IR and these tools are monolithic and mostly proprietary. So what I expect is that the design of mlir can be used in the whole ic design’s workflow instead of just frontend, at least to the synthesized netlists level. And that is not so difficult from my perspective, and I have no questions, Thank you for your reply! : )