Our architecture(TCE) can have LOTS of registers.
It seems r152019 changed some register bookkeeping data structures to 8-bit. This broke support for architectures with >255 registers.
Please revert this change or make those register-related values at least 16 bits wide.
Ughh... yeah I would have to agree here. The AMDIL backend uses more than 256 registers to model its register file correctly.
I agree. We can limit the number of physregs to 64k, but no more.
This has been changed to uint16_t in r152100.
I have reverted the commits that limited the concatenated register and instruction names to 64k. They would have caused problems for a 16k register target.
Heikki, please let me know if you are having problems with the limits enforced by TableGen now.