If I want to add some custom riscv instructions with a length of 128bit, does it support mixed compilation with 32bit instructions for llvm, and is there any relevant case for reference?
Looking forward to your reply ， Thank you .
There aren’t any extensions upstream that use instruction encodings > 32-bit, so you’d need to explore how to do this yourself (sorry, it’s not something I’ve looked at at). You can see in RISCVDisassembler.cpp, in getInstruction, the code paths assume instructions are either 32-bit or 16-bit.
@asb Thank you for your reply. As I am not sure if this can be done, so I would like to know if anyone has done similar extensions or provided some suggestions.
I will continue to explore it. Thank you again.
A similar issue exists in the RISCVMCCodeEmitter.
This patch added support for tablegen generated code to understand sizes larger than 64. [CodeEmitter] Support instruction widths > 64 bits · llvm/llvm-project@60aadd1 · GitHub
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