I would like to build some examples for ARM SVE.
I see the support for SVE is available in the AArch64 back end of the latest LLVM.
So I thought of using the latest LLVM distribution (revision 352287 from Jan 2019)
and not rely on the ARM HPC compiler from
There is SVE support in the back-end, so we can consume and generate
SVE code, though I'm not sure what completion level it is, but user
interaction with SVE is restricted to generating (asm) code snippets
by hand and passing it directly to the back-end.
There is no IR support for scalable vectors yet, though this is being
discussed with the RISC-V folks, to make sure we get something that
works for everyone.
There is no IR lowering into MIR, which will only be possible once we
know how the IR will look like.
There is no vectorisation support for scalable vectors (SVE or
otherwise), so simple loops will never be turned into SVE, even after
we have all the above. This, again, needs all the above problems to
have been tackled to be constructively worked on.
Alternatives to vectorisation would be either inline ASM (which maybe
can already be plugged into, but YMMV) or intrinsics (as covered by
the SVE ACLE) which are also not yet supported (same reason, no IR
In summary, finaliing IR support for SVE would open the other avenues
of work, and that's why we're still stuck.
Is there something I'm missing? Or do I really have to use ARM's HPC compiler?
You can also use GCC 8+, which has support for SVE vectorisation and
does a good job at it. You probably already know but, current upstream
QEMU has SVE support (user and system emulation), but it might not
have reached your distro yet.