Compiler Engineer Position (Singapore)

The Advanced Digital Sciences Center (ADSC), a University of Illinois research center ( is starting a major expansion of an ongoing project in high level synthesis. In the recent past, ADSC has published several well-received research papers in the area of high level synthesis, and we are now embarking on an ambitious expansion of that project. As such, there are available positions for PhD-level positions and BS/MS level positions with a variety of skills and areas of expertise desired. Salaries and benefits will be competitive, commensurate with the level of skill and background experience demonstrated.

General information:

The infrastructure is an LLVM-based HLS platform developed internally at ADSC that takes C/C++ language inputs and produces Verilog/SystemC HDL outputs. Top candidates will have experience in LLVM/Polly development, algorithms expertise in hardware synthesis, and/or hardware expertise in FPGA and ASIC design.

As this is a large project, there is an expectation that candidates will have a mixture of a subset of these skills; furthermore, good candidates may have demonstrated skill in development outside of the HLS area, paired with interest and desire to apply prior skills into a new area.

Specific information:

Regardless of the level of position, we are looking for people with the following areas of expertise

  • LLVM development (scheduling, register allocation, instruction combine)
  • Polly development
  • High-level synthesis, logic synthesis
  • Digital circuit design (timing closure, power optimization)
  • SystemC modeling, TLM, and virtual platform
  • Floating point optimization, range analysis
  • Python, TCL, scripting languages

Interested applicants should contact the following people for more information or to provide a resume/CV. In application material, please ensure to emphasize prior project development experience.

Deming Chen (UIUC) :
Swathi Gurumani (ADSC) :
Hongbin Zheng (ADSC) :
Kyle Rupnow (NTU) :