Conditional Register Assignment based on the no of loop iterations

Thank you for a your reply.
No i am not asking for software pipelining. my goal is different.

I am targetting a hardware with 64 element vector operations. now there are 2 scenarios;

if my loop has >=2048 iterations i use vector width=2048 and if my loop has <2048 iterations i use vector width=64. but my hardware doesnot support vector width=2048 it does support vector width=64.
now when iterations >=2048, again they are splitted into v64i32( have implemented it). till this point instruction selection is working fine.
the only difference should come in register set. the registers are same for both the scenarios but their ordering is need to be different like;
if no of iterations >=2048, ordering should be of Reg_A

here;

if no of iterations <2048, ordering should be of Reg_B

here i need is this that if no of iterations<2048 and i set vector width=64 then in this case i want my operations to be performed on Reg_B if iterations>=2048, operations to be performed on Reg_A.

i have think of several solutions to this but none worked yet??

can it be something like;

i provide support for v2048i32 in llvm and then use expand like this;

setOperationAction(ISD::LOAD , MVT::v2048i32 , Expand);

so that it can split v2048i32 into v64i32 and in instructioninfo.td i associate reg_a with it instead of reg_b there in instructioninfo.td i will use v2048i32 for >=2048 iterations and v64i32 for <2048 iterations but that v2048i32 is required to be lowered to v64i32 (in isellowering.cpp) because no support for v2048i32 in hardware. so i will use v2048i32 here just to distinguish no of iterations…

What do you say??
please help. i am seriously stuck here.

Thank you