Configuring LLVM Sparc target for Leon 3 and Leon 4 variants

At the moment I am using LLVM to target our proprietary SHAVE processor, but the Movidius “Myriad” chip also utilises a Sparc Leon for executive functions. For this I use the GCC compiler.

This all works fine, but I would like to consolidate code generation for both targets in the same LLVM derived compiler to simplify things and I have a couple of questions about the Sparc backend in LLVM I was wondering if someone could help me with.

· It is not 100% clear to me that the existing backend fully supports the Sparc V8 architecture, and the Leon variants in particular. Does anyone know whether this architecture is supported in the Sparc backend?

· How easy is it to configure the existing Sparc back-end for bi-endian code generation?

Thanks,

MartinO

Martin J. O’Riordan Email: Martin.ORiordan@movidius.com

Compiler Development Web: www.movidius.com

Movidius Ltd. Skype: moviMartinO

1st Floor, O’Connell Bridge House, d’Olier Street, Dublin 2, Ireland

· It is not 100% clear to me that the existing backend fully
supports the Sparc V8 architecture, and the Leon variants in particular.
Does anyone know whether this architecture is supported in the Sparc
backend?

Full support for v8,v8+ looks like it's getting close. Nothing
Leon-specific, but a few folks seem to be adding missing instructions
occasionally.

· How easy is it to configure the existing Sparc back-end for
bi-endian code generation?

It can already do that.

Doug

Thanks very much Doug, that is really useful information. If it’s that close I should be able to wade in and help out in completing it.

MartinO