[CUDA/NVPTX] design doc for memory space inference

As a continuation to the effort of documenting optimizations for GPGPU programs, I am sending out the design doc for another series of NVPTX-specific optimizations called memory space inference. They are already upstreamed to LLVM’s NVPTX backend (relevant code can be found here).

Again, feel free to comment.


I just want to chime in saying a huge thank you for documenting this kind of stuff.

I also wanted to suggest in general turning these design documents into ‘.rst’ format and putting them into a design document tree in the LLVM docs. Then, perhaps, referencing them from the code that implements these techniques. This kind of careful and detailed documentation is a huge benefit to the community and would help anyone starting to work on NVPTX or other GPU optimization.

Thanks again,