Custom constraints in instruction schedulers

Hello Andrew, Dave,

during review of http://reviews.llvm.org/D6054 it was suggested that I
ask you of a better approach using instruction scheduler.

What I'm trying to do

Hi Sergey,

Hello Andrew, Dave,

during review of http://reviews.llvm.org/D6054 it was suggested that I
ask you of a better approach using instruction scheduler.

What I'm trying to do
---------------------

Ensuring that ldp-stp instruction pair used to implement inlined memcpy()
have no instructions between them.

Approaches that didn't work
---------------------------

In general:

* gluing
* using TokenFactor node per load/store pair
* pseudo-instruction (couldn't implement due to the need of temporary
   registers)

I haven't followed the review, so that I don't know whether this would work for you or not. Did you consider adding a 'def' operand to your pseudo-instruction? That should allow you to allocate a register for your temporary value. Of course, this only works if the pseudo instruction is created before register allocation.

Hey Sergey,

I only learned of clustering a short time ago, but it sounds like what you're after. The MIScheduler uses clusters as one of the heuristics. The idea is to ensure that instructions remain clustered (if possible) after scheduling to ensure later peephole optimizations still work. I haven't used it, so I can't speak to the effectiveness. Hope this helps.

-Dave