Dead register (was Re: [llvm-commits] [llvm] r145819)

RegScavenger is complaining about use of an undefined register, CTR8, in
the BCTR8 instruction, in the following instance (this is from the PPC
backend):

BB#38: derived from LLVM BB %for.end50
    Predecessors according to CFG: BB#36
        %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
        %X4<def> = RLDICR %X3<kill>, 3, 60
        %X5<def> = LI8 <jt#0>[TF=4]
        %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
        %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
        MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
        BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
    Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
BB#25 BB#12 BB#16 BB#18 BB#13 BB#17

How could CRT8 be marked implicitly-defined and also dead in the same
instruction when it is clearly used in the next instruction? The code
that inserts these instructions is in SDNode
*PPCDAGToDAGISel::Select(SDNode *N) and reads:

  case ISD::BRIND: {
    // FIXME: Should custom lower this.
    SDValue Chain = N->getOperand(0);
    SDValue Target = N->getOperand(1);
    unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR :
PPC::MTCTR8;
    unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR :
PPC::BCTR8;
    Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
                                           Chain), 0);
    return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
  }

Thanks in advance,
Hal

This is the kind of sloppy liveness, I was talking about :wink:

llc -verify-machineinstrs should give you better info.

/jakob

> RegScavenger is complaining about use of an undefined register, CTR8, in
> the BCTR8 instruction, in the following instance (this is from the PPC
> backend):
>
> BB#38: derived from LLVM BB %for.end50
> Predecessors according to CFG: BB#36
> %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> %X4<def> = RLDICR %X3<kill>, 3, 60
> %X5<def> = LI8 <jt#0>[TF=4]
> %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
>
> How could CRT8 be marked implicitly-defined and also dead in the same
> instruction when it is clearly used in the next instruction?

This is the kind of sloppy liveness, I was talking about :wink:

Yea, I went looking :wink:

llc -verify-machineinstrs should give you better info.

Thanks!

-Hal

> RegScavenger is complaining about use of an undefined register, CTR8, in
> the BCTR8 instruction, in the following instance (this is from the PPC
> backend):
>
> BB#38: derived from LLVM BB %for.end50
> Predecessors according to CFG: BB#36
> %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> %X4<def> = RLDICR %X3<kill>, 3, 60
> %X5<def> = LI8 <jt#0>[TF=4]
> %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
>
> How could CRT8 be marked implicitly-defined and also dead in the same
> instruction when it is clearly used in the next instruction?

This is the kind of sloppy liveness, I was talking about :wink:

llc -verify-machineinstrs should give you better info.

Unfortunately, this just tells me what I already knew:

*** Bad machine code: Using an undefined physical register ***
- function: check
- basic block: for.end50 0x2bef428 (BB#38)
- instruction: BCTR8 %CTR8<imp-use>, %RM<imp-use>
- operand 0: %CTR8<imp-use>
LLVM ERROR: Found 1 machine code errors.

This comes from the following four statements in
PPCDAGToDAGISel::Select; what's wrong here?
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
unsigned Opc = PPC::MTCTR8;
unsigned Reg = PPC::BCTR8;
Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
                                           Chain), 0);
return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);

Thanks again,
Hal

Ping.

And, if I count correctly, I meant six statements, not four. Regardless,
this is the last remaining -verify-machineinstrs error in PPC that I've
found so far, so please help me fix it.

Thanks again,
Hal

>
> > RegScavenger is complaining about use of an undefined register, CTR8, in
> > the BCTR8 instruction, in the following instance (this is from the PPC
> > backend):
> >
> > BB#38: derived from LLVM BB %for.end50
> > Predecessors according to CFG: BB#36
> > %X3<def> = LD 0, <fi#27>; mem:LD8[FixedStack27]
> > %X4<def> = RLDICR %X3<kill>, 3, 60
> > %X5<def> = LI8 <jt#0>[TF=4]
> > %X5<def> = ADDIS8 %X5<kill>, <jt#0>[TF=8]
> > %X4<def> = LDX %X4<kill>, %X5<kill>; mem:LD8[JumpTable]
> > MTCTR8 %X4<kill>, %CTR8<imp-def,dead>
> > BCTR8 %CTR8<imp-use,kill>, %RM<imp-use>
> > Successors according to CFG: BB#23 BB#15 BB#7 BB#8 BB#9 BB#10 BB#11
> > BB#25 BB#12 BB#16 BB#18 BB#13 BB#17
> >
> > How could CRT8 be marked implicitly-defined and also dead in the same
> > instruction when it is clearly used in the next instruction?
>
> This is the kind of sloppy liveness, I was talking about :wink:
>
> llc -verify-machineinstrs should give you better info.

Unfortunately, this just tells me what I already knew:

*** Bad machine code: Using an undefined physical register ***
- function: check
- basic block: for.end50 0x2bef428 (BB#38)
- instruction: BCTR8 %CTR8<imp-use>, %RM<imp-use>
- operand 0: %CTR8<imp-use>
LLVM ERROR: Found 1 machine code errors.

This comes from the following four statements in
PPCDAGToDAGISel::Select; what's wrong here?
SDValue Chain = N->getOperand(0);
SDValue Target = N->getOperand(1);
unsigned Opc = PPC::MTCTR8;
unsigned Reg = PPC::BCTR8;
Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Other, Target,
                                           Chain), 0);
return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);

So it seems that CTR8 is being added through a call to
MachineInstr::addRegisterDead by InstrEmitter::EmitMachineNode, and this
is done for all implicitly-defined registers that don't otherwise seem
to be used. Furthermore, it seems that determining usage is tied to
looking for "glued" nodes. Changing the first MVT::Other to MVT::Glue
solved the problem.

-Hal