Declare multiple data type for a register class in tblegen

Hi everyone,

I tried to declare multiple data type [i64, i32, v2i32] for a 64 bit register class GPR. It works OK but I have one problem that is hard to find.

When I tried to map a load instruction of a v2i32 type (LOAD v2i32:$dst) to load GPR, it always generate two LOAD i32 instead of one LOAD v2i32. Any folds understand how this works?


You probably haven't called addRegisterClass in the TargetLowering constructor for the vector type. Without it added there, the type legalizer will split the vector load into components


Hi Matt,

I did call addRegisterClass in TargetLowering for all the possible types in the register. And for typecasting instructions (i32 to i64), it works. Any other possiblilities?

Try looking at the output of -debug-only=isel and see where the load is getting split up. The load isn't reaching instruction selection for your pattern to do anything

Thanks. I’m gonna try tomorrow and let you know.

Hi Matt,

I tried debug-only=isel and have some more informations.
The steps before ‘Legalized selection’( excluding it) all use v2i32 load. At the step of ‘Legalized selection’, it replaced one v2i32 load by two i32 load + shl+ or + bitcast (I have a pattern for convert from v2i32 to 2*i32). In previous steps (initial, lowered, type-legalized), they all use v2i32 load.
Can you please think of any other places where certain things have to be declared legal?


Oh, they have selection details in the end. Let me check that first…

The selection details are just instruction selections after legalization and no useful information was there as well…

My temporary solution is to use ‘Custom’ to lower it.

You should be able to see in what phase it was split. The full -debug info might be helpful, I've occasionally noticed problems where some information seems to be missing from just -debug-only=isel