Default to ARM Thumb for disassembly?

I’m debugging a Cortex-M0+ target via the gcc-generated ELF file. By default, lldb disassembles what it thinks is ARM instructions, but really they’re Thumb:

(lldb) dis
->  0x294: stmdami r5!, {r2, r5, r8, r11, lr}
    0x298: addmi  r11, r1, #112, #10
    0x29c: blmi   0x9342cc
    0x2a0: andhs  r1, r0, #196, #28
    0x2a4: movwle r4, #0x32a3
    0x2a8: bne    0x68cebc
    0x2ac: umullseq r0, r2, r2, r8
    0x2b0: .long  0xfc2af001                ; unknown opcode
(lldb) dis -A thumb
->  0x294: ldr    r1, [pc, #0x90]
    0x296: ldr    r0, [pc, #0x94]
    0x298: push   {r4, r5, r6, lr}
    0x29a: cmp    r1, r0
    0x29c: beq    0x2b4
    0x29e: ldr    r3, [pc, #0x90]
    0x2a0: subs   r4, r0, #0x3
    0x2a2: movs   r2, #0x0
    0x2a4: cmp    r3, r4
    0x2a6: blo    0x2b0
    0x2a8: adds   r3, #0x3
    0x2aa: subs   r2, r3, r0
    0x2ac: lsrs   r2, r2, #0x2
    0x2ae: lsls   r2, r2, #0x2
    0x2b0: bl     0x1b08

Is there any way to default to Thumb?

lldb does not have an equivalent to gdb’s setting (debugging - GDB doesn't disassemble program running in RAM correctly - Stack Overflow).

I see a lot of code checking for Thumb so we do handle it in at least some situations. I’d have to reproduce to see exactly why this doesn’t work (e.g. does the debug stub here report the PC with the bottom bit cleared for some reason).

And I see you made a longer post with more info and I do intend to read that when I have time, it will probably give more clues.

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Interesting, I got the exact same results for JITed Thumb code, but for me it was expected since my executor binary was build as ARM and not Thumb.

Did you try and build with Clang? In a quick test it does work for me:

> cat test-arm-thumb.c
int main() { return 0; }

> clang -g -o test-arm test-arm-thumb.c
> clang -mthumb -g -o test-thumb test-arm-thumb.c

(lldb) version
lldb version 15.0.0-custom

(lldb) dis
    0x103f4 <+0>:  sub    sp, sp, #4
    0x103f8 <+4>:  movw   r0, #0x0
    0x103fc <+8>:  str    r0, [sp]
->  0x10400 <+12>: movw   r0, #0x0
    0x10404 <+16>: add    sp, sp, #4
    0x10408 <+20>: bx     lr

(lldb) dis
    0x205ac <+0>: sub    sp, #0x4
    0x205ae <+2>: movs   r0, #0x0
    0x205b0 <+4>: str    r0, [sp]
->  0x205b2 <+6>: add    sp, #0x4
    0x205b4 <+8>: bx     lr
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